1. Field of the Invention
This invention is related to the field of simulation of digital circuit designs.
2. Description of the Related Art
An important part of digital circuit design methodology is verification of the digital circuit design. A thorough verification effort can ensure, or at least significantly improve the odds, that the digital circuit design will actually work when fabricated (e.g. as an integrated circuit or a combination of integrated circuits and/or discrete elements). A large part of the verification is typically performed by simulating the design in a simulator, applying various test stimuli and determining if the circuit is behaving as expected.
The design is typically expressed in a hardware design language (HDL) such as Verilog or VHDL. The HDL description of the design can be read by a simulator to simulate the design (or the description can be compiled into a model that the simulator can operate on to simulate the design). The simulators can be event driven simulators, cycle-based simulators, etc. These simulators will generically be referred to herein as HDL simulators, because they simulate the design based on the HDL description. The smallest element in the simulation is a logic gate (e.g. NAND, NOR, AND, OR, inverter, etc.). The logic gates can be realized in transistors, for example, but the transistors are not modeled for simulation in the HDL simulator. Instead, the logic gate is modeled. Other simulators (e.g. SPICE or SPICE-like simulators) can be used to perform simulation at the transistor level.
In HDL simulation, the various signals in the design may take on digital values (zero and one), and may also take on an X value. The X value is an undetermined value, and can occur in a simulation if an uninitialized memory location, flop, etc. is read. The X value can also occur if an input is not driven with a value. In some simulators, a high impedance value (or “Z” value) is also supported for a signal that has a weak pullup or pulldown when not actively driven.
HDL simulators that support the X value and are implemented according to an HDL standard such as the Verilog standard may be propagating the X value (representing an unknown value) even though the actual circuitry will realize a known value (e.g. binary 0 or 1). This behavior of the HDL simulator is referred to as X-pessimism. That is, unless the simulator can be certain that the unknown (i.e. X) value does not propagate from an input to an output of an element in the simulation, the unknown value is propagated as the output. For example, an AND gate having an X input and a zero input is guaranteed to have a zero output and thus the X is not propagated. However, if the other input to the AND gate is a one, the output of the AND gate is unknown and the X is propagated. In some cases, the larger circuit formed from multiple logic gates would lead to a known (non-X) output even with a particular (i.e. X) input value. However, the HDL simulation can still propagate X's depending on the underlying logic gates, because the individual gates are evaluated by the simulators according to the HDL standard (e.g. Verilog standard).
It is an increasing trend in the industry to use “uninitialized” memory elements such as flops wherever possible in the design. That is, the memory elements may not be reset to a known value. By avoiding the circuitry associated with resetting/initializing the memory element, the memory element may be implemented with less circuitry and may thus occupy less silicon area. However, coupled with the X-pessimism of the simulators as discussed above, the increased use of uninitialized memory elements often causes verification engineers to spend significant amounts of time analyzing X propagations that occur due to X-pessimism (i.e. the unknown state present in simulation and not present in the fabricated circuit).